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Cake day: June 15th, 2023

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  • The limit on Moore’s Law has been more to the economic side than actually packing transistors in.

    The reason why those economic limits exist is because we’re reaching the limit of what’s physically possible. Fabs are still squeezing more transistors into less space, for now, but the cost per transistor hasn’t fallen for some time, IIRC about 10nm thereabouts is still the most economical node. Things just get difficult and exponentially fickle the smaller you get, and at some point there’s going to be a wall. Of note currently we’re talking more about things like backside power delivery than actually shrinking anything. Die-on-die packaging and stuff.

    Long story short: Node shrinks aren’t the low-hanging fruit any more. Haven’t been since the end of planar transistors (if it had been possible to just shrink back then they wouldn’t have engineered FinFETs) but it’s really been taking up speed with the start of the EUV era. Finer and finer pitches don’t really matter if you have to have more and more lithography/etching/coating steps because the structures you’re building are getting more and more involved in the z axis, every additional step costs additional machine time. On the upside, newer production lines could spit out older nodes at pretty much printing press speed.




  • VESA Adaptive-Sync goes back to the eDP stardard, 2009. AMD simply took that and said “Hey why aren’t we doing that over external DisplayPort”. And they did.

    So instead of over-engineering a solution that nobody asked for to create vendor lock-in nobody (but fanboys with Stockholm Syndrome) want they exposed functionality that many many panels already had, anyway, because manufactures don’t use completely different control circuitry for laptop (eDP) and stand-alone monitors.

    And, no, nvidia’s tech is not superior. From what I gather they have stricter certification requirements but that’s it.